Volume 25, No. 6 June 2000
A Publication of the Materials Research Society
© Copyright 2000
Materials Research Society
All rights reserved
DEFECTS AND DIFFUSION IN SILICON TECHNOLOGY
Defects and Diffusion
in Silicon Technology, 14
T.E. Haynes, Guest Editor
Scaling Transistors into the Deep-Submicron
Regime, 18
P.A. Packan
Diffusion Mechanisms and Intrinsic Point-Defect
Properties in Silicon, 22
H. Bracht
Intrinsic Point Defects and Their Control
in Silicon Crystal Growth and Wafer Processing, 28
R. Falster and V.V. Voronkov
Advanced Gettering Techniques in ULSI Technology,
33
A.A. Istratov, H. Hieslmair, and E.R. Weber
Enhanced Diffusion in Silicon Processing,
39
N. Cowern and C. Rafferty
Simulation of Defects and Diffusion Phenomena
in Silicon, 45
M.E. Law, G.H. Gilmer, and M. Jaraíz
MRS NEWS
JMR Launches Electronic Submission Database, 51
ABSTRACTS
Abstracts for July 2000 Journal of Materials Research, 59
DEPARTMENTS
Research/Researchers, 4
Washington News, 11
Resources , 13
Career Clips, 51
Library:
Aerosol Processing of Materials, T.T. Kodas and M. Hampden-Smith,
reviewed by T.L. Ward
Advanced Computing in Electron Microscopy, E.J. Kirkland, reviewed
by F. Ross., 52
Classified , 62
Advertisers
in This Issue , 64
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On the Cover:
As silicon microelectronics have advanced,
the vertical and lateral dimensions of the devices have decreased
to the point that understanding and controlling defects and diffusion
in silicon have become an important challenge. Far right: Calculations
of the potential contours for transistors with 0.1-µm gates
in the "off" state. For a properly designed transistor
with shallow junctions (far right, top), there is no current
flow in the off state, but when the junctions are too deep (far
right, bottom), the potential gradient under the gate is too
small to completely eliminate current flow. Bottom image: Modeling
diffusion at minute length scales requires the ability to simulate
complex interactions between point and extended defects as well
as events that span many orders of magnitude in time. The four
panels show a time-ordered sequence from an atomistic simulation
of an 800°C anneal following the ion implantation of 1014
Si ions per cm2 at 5 keV into silicon. The region shown is a
50-nm-sided cube, and from left to right, the times are 0 s (ramp-up),
1 s, 40 s, and 250 s. Red and blue spheres represent silicon
self-interstitials and vacancies, respectively, produced by atomic
collisions as the ions are stopped in the crystal. At 1 s, there
is already a dramatic reduction of the damage, mainly resulting
from the annihilation of interstitials with vacancies, and two
distinct defect bands have emerged (vacancy clusters near the
surface and interstitials deeper into the bulk). After 40 s,
a denuded region appears near the surface, which is a strong
sink for defects. Finally, the remaining interstitials undergo
an Ostwald ripening process that leads to growth of a few large
{311} defects at 250 s. Center image: The atomic-resolution micrograph
shows an image of an actual {311} defect viewed end-on. The symbols
superimposed on this image illustrate the basic concept of the
kinetic Monte Carlo approach used to generate these simulations,
wherein only the atoms that are in defects are tracked. See the
technical theme that begins on page 14. Images courtesy of Paul
Packan, George Gilmer, Martin Jaraíz, and David Eaglesham.
