As the 1998 Spring Meeting entered its penultimate day, several symposia began their last day of presentations.

Jim Harper

Michael Riordan

Symposium X concluded with two very interesting talks again dealing with historical issues in semiconductors. The first was given by Jim Harper of IBM on "Silicon Chip Interconnections from Aluminum to Copper." Harper described the evolution of interconnect processing at IBM and in the industry in general beginning with the liftoff technique in the 70s, metal Reactive Ion Etching (RIE) in the 80s to the Damascene process late 80s to the dual Damascene process to BEDL at present and in the very near future particularly for Cu interconnects. He also discussed the use of W for vertical structures between interconnects. While Cu has always been inherently better in terms of conductive properties, it has a catastrophic effect on transistors. In additionm there is no plasma etching method for Cu. Hence thus far, Al alloyed with Cu has been used. Recently, however, it has been possible eto encapsulate Cu to eliminate any contact with Si thus paving the way for its use. It is likely that in future Cu will be alloyed with other metals for optimum properties (The IBM website has some interesting micrographs). Harper also described the National Technology Roadmap for Semiconductors which lists requirement by the year 2006 as well as beyond 2006 (weblink: www.sematech.org). Materials issues are prominant among the requirements listed. The second talk in this symposium was given by Michael Riordan of Stanford Linear Accelerator Center on "The Road to Silicon was paved with Germanium." Here, Riordan presented convincing evidence that Ge played a crucial role in the development of the silicon semiconductor technology, right from the beginnings of the transistor at Bell Labs. The very first transistor and the first IC used Ge.

Within Symposium BB, Computation and Mathematical Models of Microstructural Evolution, there were two interesting invited talks in the morning dealing with Multiscale Models. The first by Jeremy Broughton (Naval Research Lab) on an algorithm for simulation of systems on all length scales. The algorithm appears to work well for semiconducting and insulating systems, and development is under way for metallic systems. The second talk on "Simulation of the Growth of Heterostructures" was by John Harding of University College, London. One of the problems in heterostructures is stresses in films due to mismatch. This was considered in the work presented here in semiconducting systems as well as in ceramics.

B. Fultz (Caltech) reported on improved alloys for Ni-MH Batteries in Symposium H. Ni metal hydride batteries though new are widely used now. There is however plenty of room for improvements in lifecycle by optimizing electrochemical properties. The way to improve cycle life would be to slow down kinetics to slow down deterioration. One way to do that would be to alloy LaNi5 which is the material used at present. A series of LaNi5-xMx alloys were studied. LaNi5-xGex did well in tests. Overall, studies showed that La should be replaced with Mischmetal with Ce additions. Two compositions that did well were Mm1.0Ni4.4Ge0.4In0.2 and Mm1.0Ni4.4Ge0.4Sn0.2.

There was a talk in Sympoaium B on "Grain Engineering: A manufacturable approach for high performance poly thin film transistor fabrication" by Thomas Sigmon. Excimer laser annealing was used to control the microstructure of the polysilicon thin films, wherein grain size can have a significant role on performance and device-to-device uniformity of thin film transistors. A four mask TFT process using gas immersion laser doping was used to evaluate effect of microstructure on TFT performance.

This was also the third and final day of poster sessions. Two poster awards were announced:

D12.8 A novel system for semiconductor contamination analysis, B. Lagel (Robert Gordon Univ., Aberdeen, UK)

T5.9 In-Situ Nanoindentation of electrochemically modified surfaces, Sean Corcoran (Hysitron Inc.)