As we approach the 21st Century, the feature size of microelectronic devices enters the deep submicron regime. The process integration and structure-properties control of the multi-level metal circuits demand an interdisciplinary interaction among manufacturing engineers and development/research scientists.
This symposium will address the following topics related to the future ULSI technology:
* National technology road map for ULSI metallization: e.g., projection of performance requirements and materials limits
* Process integration of multilevel metal (MLM) interconnect, e.g., planarization, via filling, liner, low-K dielectrics, yield analysis
* Metrology of submicron structures: e.g., adhesion, local stress, defect detection, grain boundary analysis
* Cu-based metallization vs. Al-based metallization, e.g., electromigration behavior of Al(Cu) alloy vs. Cu(Sn) alloy
* Modeling and accelerated testing of reliability
* Contact and interfaces, e.g., shallow silicide contacts, contact to SOI, via contact resistance, contact to compound semiconductors
Partial list of invited speakers: T.E. Seidel (SEMATECH), 0.1 um Technology and SIA Road Map; D. Fraser (Intel Corporation), The National Technology Roadmap for Back-End-of-Line; T.H. Ning (IBM), 0.1 um Technology and BEOL; A.K. Sinha (Applied Materials), Interconnects and Tools; C.Y. Lu (Vanguard Semiconductor, Taiwan), The Challenge of ULSI Semiconductor Memory Interconnection Technology; R.S. Sorbello (University of Wisconsin), Theory of Electromigration; R.W. Vook (Syracuse University), In-Situ Study of Electromigration in Cu Films; C.K. Hu (IBM), Electromigration Behavior of Cu(Sn) Alloy Films; W.D. Nix (Stanford University), Metrology of Film Adhesion; G.S. Cargill III (Columbia University), X-Ray Microdiffraction for VLSI; L.T. Shi (IBM), Stress Modeling of Asymmetrical via Line Structures; I. Yamada (Kyoto University), Deposition of Metal on Si by Ionized Cluster Beam; A.E. Kaloyeros (SUNY-Albany), CVD of Cu; M. Eizenberg (Technion), CVD TiN Liner; S.P. Murarka (Rensselaer Polytechnic Institute), CMP of Cu; D.N. Lee (Seoul National University), Textures in Cu Electrodeposits; R.T. Tung (AT&T Bell Laboratories), Shallow Silicide Contacts; and M. Takai (Osaka University), Nuclear Microprobe Analysis of Silicides; S. Ogawa (Matsushita), Application of Ti,Co Silicides to Shallow Junctions in ULSI
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Symposium Organizers
K.N. Tu
Department of Materials Science
and Engineering
University of California at Los Angeles
Los Angeles, CA 90095-1595
Phone (310) 206-4838
Fax (310) 206-7353
kntu@seas.ucla.edu
J.M. Poate
AT&T Bell Laboratories
P.O. Box 636
Murray Hill, NJ 07974-0636
Phone (908) 582-3462
Fax (908) 582-4228
jmp@physics.att.com
J.W. Mayer
Center for Solid State Science
Arizona State University
Tempe, AZ 85287-1704
Phone (602) 965-9601
Fax (602) 965-9004
ifjwm@asuvm.inre.asu.edu
L.J. Chen
Department of Materials Science
and Engineering
National Tsing Hua University
Hsinchu, Taiwan 30043
R.O. China
Phone (886) 35-718328
Fax (886) 35-718328
ljchen@mse.nthu.edu.tw
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