Future CMOS devices will require aggressive Tinv scaling for performance gain and reduced gate leakage for low power consumption. Traditional nitrided-SiO 2 (SiON) dielectrics have been scaled to a point where further physical scaling results in unacceptably high-leakage current and degrades carrier mobility in the channel. While effort is still ongoing to investigate scaling options for SiON dielectrics, a more intense effort is under way to find a high-k replacement for SiON dielectrics. Although the intuitive approach of replacing the gate dielectric alone with high-k dielectrics─while retaining the well-tested poly-Si electrodes─helps to reduce the gate leakage, it suffers from a host of issues. pFET gates in such stacks exhibit a large threshold voltage shift, and scalability of such stacks is questionable due to large poly-Si depletion (~ 0.3-0.5 nm). Replacing poly-Si with metal electrodes is attractive to overcome these impediments and meet high-performance technology targets. However, identifying Si-band edge p+ and n+ metals and integrating them in a CMOS flow poses enormous challenges. Other seemingly easy and elegant approaches like fully silicided gate electrodes have been stymied by lack of work-function control. Many of these challenges are centered on candidate materials selection, their processing, and the role of interfaces formed between the various layers, which dominate the final electrical behavior and reliability of the gate stack. Unlike more-established Si-based dielectrics, metal-oxide-based high-k dielectrics are poorly understood. Due to the strong process-structure-property correlation in these dielectrics, they are prone to numerous defects arising from impurity incorporation, lack of thermal and chemical stability, oxygen vacancies, etc. Such defects have a significant impact on the reliability of gate stacks─in terms of lifetime (Tbd/Qbd) and threshold voltage stability (PBTI/NBTI). This symposium will focus on gaining fundamental insight into these critical issues. Contributions are solicited in the above and related areas that enhance fundamental understanding of future gate stack materials, structure, property interactions, and their impact on electrical properties and reliability.

Proposed session topics include, but are not limited to:

• Materials, deposition mechanisms, and precursor selection
• Chemical/thermodynamic stability of electrode/dielectric/semiconductor interfaces
• Kinetics of interface reactions and interface engineering
• Band-structure and work-function determination
• Impact of process integration on gate stack stability
• Nitridation mechanisms and other scalability approaches
• Atomic-scale structural characterization
• Metallic and gaseous diffusion through gate stacks
• Current leakage and mobility-detraction mechanisms
• Advanced electrical characterization techniques
• Charge trapping, NBTI, and defect-characterization techniques
• Reliability and impact of hot carriers

Invited speakers include: Yasushi Akasaka (SELETE), Yves Chabal (Rutgers Univ.), M. Copel (IBM), P. Majhi (Sematech), J.W. McPherson (Texas Instruments), Manuel Quevedo Lopez (Sematech), L. Ragnarson (IMEC, Belgium), and Akiyoshi Uedono (Univ. of Tsukuba, Japan).

Raj Jammy
IBM T.J. Watson Research Center
P.O. Box 218 (1101 Kitchawan Rd., Rte. 134)
Yorktown Heights, NY 10598
Tel 914-945-3175
Fax 914-945-2141
jammyr@us.ibm.com

Ajit Shanware
Texas Instruments, Inc.
MS 3740
13560 N. Central Expwy.
Dallas, TX 75243
Tel 972-995-3494
Fax 972-995-3075
ajit-shanware@ti.com

Veena Misra
North Carolina State University
Dept. of Electrical & Computer Engineering
Box 7911
Raleigh, NC 27695
Tel 919-515-7356
Fax 919-515-3027
vmisra@ncsu.edu

Yoshitaka Tsunashima
Toshiba Corporation
8 Shisugita-cho
Isogo-ku, Yokohama 235-8522, Japan
Tel 81-45-770-3681
Fax 81-45-770-3577
yoshitaka.tsunashima@toshiba.co.jp

Stefan De Gendt
IMEC, UCP-VMT
Kapeldreef 75, B-3001
Leuven, Belgium
Tel 32-16-28-1386
Fax 32-16-28-1214
stefan.degendt@imec.be