Chairs
| Paul R. Besser |
|
Advanced Micro Devices, Inc. |
| Andrew J. McKerrow |
|
Texas Instruments, Inc. |
| C. P. Wong |
|
Georgia Institute of Technology |
| Joost Vlassak |
|
Harvard University |
| Francesca Iacopi |
|
IMEC |
Symposium Support
Advanced Micro Devices
*Applied Materials, Inc.
Texas Instruments
Tokyo Electron America
*Spring Exhibitor
Proceedings
to be published in
both book form and online
(see ONLINE PUBLICATIONS at www.mrs.org)
as volume 863
of the Materials Research Society
Symposium Proceedings Series.
* Invited paper
TUTORIAL
Wafer Level Packaging--Materials, Process, and Reliability
Monday March 28, 2005
1:00 PM - 5:00 PM
Room 2004 (Moscone West)
Wafer-Level Packaging (WLP) has gained momentum in the small chip arena, driven by needs for cost reduction, form-factor shrinkage, and enhanced performance. Advantages in performing burn-in and test at the wafer level will lower the IC cost and resolve the known good die (KGD) issues that are concerns to the electronic industry. WLP will merge the front-end IC fabrication with the back-end discrete packaging, and provide a paradigm shift in the electronic packaging industry. This course will provide an overview of the recent advances on WLP, the advantages and challenges in term of materials (conventional polymers as well as nanofunctional materials), processes (with ultra fine pitch flip chip interconnects), and reliability in this new packaging technologies.
COURSE OUTLINE:
* Overview of Electronic Packaging: Present and Future Trends
* Definition of Wafer-Level Packaging
* Market Drivers for WLP
* Overview of Various WLP Configurations and Process Techniques in the Industry
* Barriers and Challenges with WLP Technologies
* Fundamentals of Polymers and their Physical and Mechanical Properties and Measurements
* Overview of Inorganic and Organic Polymers for Electronic Packaging
- Silicon Dioxides, Nitrides & Oxynitrides
- Epoxies, Silicones, Polyimides, Silicone-Polyimides, Polyurethanes
- Benzocyclobutenes, Parylenes, BT Resins, Sycars, Polyesters, High Temperature &
Liquid-Crystal Polymers, Low-k, Low Loss and Nanofunctional and Foam Materials.
* Recent Advances on Low Cost Flip Chip: Materials, Processes, and Reliability
* Lead-free Interconnect Alternative Materials- Electrically Conductive Adhesives
* Next Generation WLPs This tutorial will be of interest to engineers, scientists, and managers involved in the design, process, and manufacturing of IC electronic components, modules, and hybrid packaging, as well as electronic material suppliers involved in materials manufacturing and research & development.
Instructors:
C. P. Wong, Georgia Institute of Technology
Luu Nguyen, National Semiconductor Corp.
SESSION B1: Characterization of Low-K Dielectrics
Chairs: Andrew McKerrow and Todd Ryan
Tuesday Morning, March 29, 2005
Room 2004 (Moscone West)
8:30 AM *B1.1
Fracture and Mechanical Behavior in Thin-Film Interconnect
Structures: Challenges for Next Technology Nodes. Reinhold
Dauskardt, Department of Materials Science and Engineering,
Stanford University, Stanford, California.
9:00 AM B1.2
A New Technique for the Characterization of the Adhesion in Patterned Films. Ibon Ocana1, Jon Molina1, Diego Gonzalez1, M. Reyes Elizalde1, J. Manuel Sanchez1, J. Manuel Martinez-Esnaola1, Javier Gil-Sevillano1, Tracey Scherban2, Daniel Pantuso2, Brad Sun2, Jessica Xu2, Barbara Miner2, Jun He2 and Jose A. Maiz2; 1CEIT (Centro de Estudios e Investigaciones Tecnicas de Gipuzkoa) and TECNUN (University of Navarra), San Sebastian, Gipuzkoa, Spain; 2Intel Corporation, Hillsboro, Oregon.
9:15 AM *B1.3
Mechanics of Advanced Interconnect Structures. Zhigang
Suo, Division of Engineering and Applied Sciences, Harvard
University, Cambridge, Massachusetts.
9:45 AM B1.4
Mechanical Properties of Porous MSQ Films: Impact of the Porogen Loading and Matrix Crosslinking. Frederic Ciaramella1, Vincent Jousseaume1, Sylvain Maitrejean1, Bruno Remiat1, Marc Verdier2, Maurine Montagnat2 and Gerard Passemard3; 1CEA-LETI, Grenoble, France; 2LTPCM, Grenoble, France; 3STMicroelectronics, Grenoble, France.
10:00 AM BREAK
10:30 AM B1.5
High-temperature Nanoindentation Measurement for Hardness and Modulus Evaluation of Low-k Films. Jiping Ye1, Nobuo Kojima1, Satoshi Shimizu1 and James M. Burkstrand2; 1Research Dept., Nissan ARC Ltd., Yokosuka, Japan; 2Hysitron, Inc., Minneapolis, Minnesota.
10:45 AM B1.6
Depth-profiling Pore Morphology in Nanoporous Thin Films
Using Positronium Annihilation Lifetime Spectroscopy. Richard
S. Vallery1, Hua-Gen Peng1, William
E. Frieze1, David W. Gidley1, Darren
Moore2 and Richard J. Carter2; 1Physics,
University of Michigan, Ann Arbor, Michigan; 2LSI
Logic Corporation, Gresham, Oregon.
11:00 AM B1.7
Linear versus Star Shaped Porogen Effects on Thin Film Pore
Structure: X-ray Porosimetry and Neutron Scattering Studies.
Hae-Jeong Lee1, Christopher L. Soles1,
Bryan D. Vogt1, Da-Wei Liu1, Wen-li Wu1,
Eric K. Lin1, Ho-Cheol Kim2, Victor Lee2,
Teddie Magbitang2, Phillip Brock2, Willi
Volksen2 and Robert D. Miller2; 1Polymers
Division, National Institute of Standards and Technology, Gaithersburg,
Maryland; 2IBM Research Division, Almaden Research
Center, San Jose, California.
11:15 AM B1.8
Solid State MAS NMR Spectroscopic Characterization of Plasma
Damage and UV Modification of Low k Dielectric Films. Thomas
Abell1, Kristof Houthoofd2, Francesca
Iacopi3, Piet Grobet2 and Karen Maex3; 1Intel
at IMEC, Leuven, Belgium; 2Department of Agriculture,
Katholic University Leuven, Leuven, Belgium; 3IMEC,
Leuven, Belgium.
11:30 AM B1.9
Novel Electrical Metrology for Microcharacterization of
Low-k Dielectrics. Vladimir V. Talanov, Robert L.
Moreland, Andre Scherz, Bin Ming and Andrew R. Schwartz; Neocera,
Inc., Beltsville, Maryland.
SESSION B2: Low-K Dielectrics: Integration Issues
Chairs: Reinhold Dauskardt and Francesca Iacopi
Tuesday Afternoon, March 29, 2005
Room 2004 (Moscone West)
1:30 PM *B2.1
Nanoporous Materials Integration into Advanced Microprocessors. E. Todd Ryan1, Cathy Labelle1, Nicholas C. M. Fuller2, Satya V. Nitta2, Griselda Bonilla2, Kenneth McCullough2, Charles Taft2, Hong Lin2, Bum Ki Moon3, Andrew Simon2, Eva Simonyi2, Mary Zaitz2, Kelly Malone2, Muthumanickam Sankarapandian2, Zijian Li4, Shuang Li4, Yushan Yan4, Junjun Liu5 and Paul S. Ho5; 1Advanced Micro Devices, Hopewell Junction, New York; 2IBM Microelectronics, Semiconductor Research and Development Center, Hopewell Junction, New York; 3Infineon Technologies, Hopewell Junction, New York; 4Department of Chemical Engineering, University of California, Riverside, California; 5Laboratory for Interconnect and Packaging, University of Texas, Austin, Texas.
2:00 PM B2.2
The Interaction of Hydrogen Plasmas with Ultralow-k Porous pSiCOH Dielectrics. Alfred Grill, Victoria Sternhagen and Vishnubhai Patel; IBM - T.J. Watson Research Center., Yorktown Heights, New York.
2:15 PM B2.3
Double-Layered Structure of Surface Modification of Low-k
Dielectrics Induced by He Plasma. Ken-ichi Yanai,
Tadayoshi Hasebe, Kouji Sumiya, Seiki Oguni and Kazuhiro Koga;
Consortium for Advanced Semiconductor Materials and Related
Technologies, Kokubunji-shi, Tokyo, Japan.
2:30 PM B2.4
Nanoscale Observation of Dielectric Damage to Low k MSQ Interconnects from Reactive Ion Etching and Ash Treatment. Todd S. Gross1, Shaoning Yao1 and Sri Satyanarayana2; 1Mechanical Engineering, University of New Hampshire, Durham, New Hampshire; 2SEMATECH, Austin, Texas.
2:45 PM B2.5
Surface Pore-Sealing in Porous MSQ Low-k Film using NH3 Plasma Treatment. Weide Wang1, Dongzhi Chi1, Jun Liu1, Lei Wang1, Soojin Chua1, David W. Gidley2 and Albert F. Yee3; 1Institute of Materials Research & Engineering, Singapore, Singapore; 2Department of Physics, University of Michigan, Ann Arbor, Michigan; 3Department of Chemical Engineering & Materials Science, University of California, Irvine, California.
3:00 PM BREAK
3:30 PM B2.6
First Pass Study of Surface Modified Porous Low-k by Ion Implantation for Zero Thickness Barrier Requirement of Cu/MSQ/Si Stacks in Copper Metallization Scheme. Alok Nandini U. Roy, Zubin P. Patel and H. Bakhru; Physics, SUNY, Albany, Albany, New York.
3:45 PM B2.7
Observation of Intrusion Rates of Hexamethyldisilazane during Supercritical Carbon Dioxide Functionalization of Triethoxyfluorosilane. P. M. Capani1, B. P. Gorman1, R. F. Reidy1, D. W. Mueller2,1, E. R. Walter2, P. D. Matz3, J. T. Rhoad4 and E. L. Busch4; 1Materials Science and Engineering, University of North Texas, Denton, Texas; 2Physics, University of North Texas, Denton, Texas; 3Silicon Technology Development, Texas Instruments, Inc, Dallas, Texas; 4SEMATECH, Austin, Texas.
4:00 PM B2.8
Supercritical Pore Sealing of Low-κ Films. P.
K. Nerusu1, R. F. Reidy1, D. W. Mueller2,1,
P. M. Capani1, P. D. Matz4, E. L. Busch3 and
J. T. Rhoad3; 1Materials Science and
Engineering, University of North Texas, Denton, Texas; 2Physics,
University of North Texas, Denton, Texas; 3SEMATECH,
Austin, Texas; 4Silicon Technology Development,
Texas Instruments, Inc., Dallas, Texas.
4:15 PM B2.9
The Deposition of Alkylmonochlorosilane Sealing Layers on Porous Methylsilsesquioxane Films Using Supercritical CO2. Bo Xie and Anthony Muscat; Chemical & Environmental Engineering, University of Arizona, Tucson, Arizona.
4:30 PM B2.10
A Cross-linkable Poly(p-xylylene) Derivative to Protect
Ultra-Low κ Dielectrics. Brad P Carrow1,
Jay J. Senkevich1, Toh-Ming Lu2, Timothy
S. Cale2, Yunqing Chen2 and Hassaram
Bakhru3; 1Brewer Science Inc., Rolla,
Missouri; 2Department of Physics, Applied Physics,
and Astronomy, Rensselaer Polytechnic Institute, Troy, New
York; 3Department of Physics, SUNY-Albany, Albany,
New York.
4:45 PM B2.11
Integration of a Polymer Etch Stop Layer in a Porous Low K MLM Structure. Gregory C. Smith1, Neil Henis1,4, Richard McGowan1,4, Brian White1,2, Matthias Kraatz1,5, Sri Satyanarayana1, Sharath Hosali1, Youfan Liu1,3 and Klaus Pfeifer1; 1SEMATECH, Austin, Texas; 2Advanced Micro Devices, Austin, Texas; 3Intel Corporation, Phoenix, Arizona; 4Freescale Semiconductor, Austin, Texas; 5University of Texas, Austin, Texas.
SESSION B3: Low-K Dielectrics: Process and Integration Issues
Chairs: Ting Tsui and Joost Vlassak
Wednesday Morning, March 30, 2005
Room 2004 (Moscone West)
8:30 AM B3.1
The Pore Structure and Integration Performance of a Porous
CVD Ultra Low k Dielectric. Youfan Liu1,
Andreas Knorr2, Wen-Li Wu3, David Gidlui4 and
Bernd Kastenmeier5; 1Intel Assignee at
SEMATECH, Austin, Texas; 2Infineon Assignee at SEMATECH,
Austin, Texas; 3NIST, Gaithergburg, Maryland; 4University
of Michigan, Ann Arbor, Michigan; 5IBM Assignee
at SEMATECH, Austin, Texas.
8:45 AM B3.2
Ultra Low K Pecvd Porogen Approach: Matrix Precursor Comparison and Porogen Removal Treatment Study. Laurent Favennec1, Vincent Jousseaume2 and Vincent Rouessac3; 1STMicroelectronics, Crolles, France; 2CEA / Leti, Grenoble, France; 3IEM, Montpellier, France.
9:00 AM B3.3
Film Properties and Integration Performance of a Nano-Porous
Carbon Doped Oxide. Lester D'Cruz, Sang Ahn, Yi
Zheng, Josephine Chang, Nagarajan Rajagopalan, Thomas Nowak,
Alex Demos, Girish Dixit, Derek Witty and Hichem M'Saad; Dielectric
Systems and Modules, Applied Materials, Inc, Santa Clara, California.
9:15 AM B3.4
Determining Pore Structure and Growth Mechanisms in Templated
Nanoporous Low-k Films. Hua-Gen Peng1,
Richard S. Vallery1, Ming Liu1, David
W. Gidley1 and Jin-Heong Yim2; 1Physics,
University of Michigan, Ann Arbor, Michigan; 2Materials
Lab, Samsung Advanced Institute of Technology (SAIT), Yongin-Si,
Gyeonggi-Do, South Korea.
9:30 AM B3.5
Nanometer-scale Pore Formation in a Polyphenylene Low-k Dielectric. Michael S. Silverstein1, Barry J. Bauer2, Ronald C. Hedden2, Hae-Jeong Lee2 and Brian G. Landes3; 1Materials Engineering, Technion - Israel Institute of Technology, Haifa, Israel; 2Polymers Division, National Institute of Standards and Technology, Gaithersburg, Maryland; 3Dow Chemical Company, Midland, Michigan.
9:45 AM BREAK
10:15 AM *B3.6
Channel Cracking in Low-k Interconnect Structures. T. M. Shaw1, Xiao Hu Liu1, Michael Lane1, Robert Rosenberg1, Sarah L. Lane2, James Doyle1, Darryl Restaino2, Steven Vogt2 and Daniel Edelstein1; 1IBM Research, Yorktown Heights, New York; 2IBM Microelectronics, Hopewell Junction, New York.
10:45 AM B3.7
The Size Effect of Nanoparticular Porogen on the Mechanical Properties of Nanoporous Ultra-low Dielectric Materials. Sung-Kyu Min1, Jae Jin Shin1, Se Jung Park1, Bongjin Moon2, Do Young Yoon3 and Hee-Woo Rhee1; 1Department of Chemical & Biomolecular Engineering, Sogang University, Seoul, South Korea; 2Department of Chemistry, Sogang University, Seoul, South Korea; 3Department of Chemistry, Seoul University, Seoul, South Korea.
11:00 AM B3.8
Fracture Property Improvements of a Nanoporous Thin Film Via Post Deposition Bond Modifications. Jeannette M. Jacques, Ting Y. Tsui, Andrew J. McKerrow and Robert Kraft; Silicon Technology Development, Texas Instruments, Inc., Dallas, Texas.
11:15 AM B3.9
Effects of UV-Cure on Mechanical, Physical and Electrical Properties of Microporous SiOC:H Dielectric Films. Francesca Iacopi1, Carlo Waldfried2, Thomas J. Abell1,3, Eric P. Guyer4, Brenda Eyckens1, Youssef Travaly1, Timo Sajavaara1,5, David M. Gage4, Gerald Beyer1, Ivan Berry2, Reinhold H. Dauskardt4 and Karen Maex1,6; 1IMEC, Leuven, Belgium; 2Axcelis Technologies, Rockville, Maryland; 3Intel Corp., Santa Clara, California; 4Materials Science and Engineering, Stanford University, Stanford, California; 5IKS, Katholieke Universiteit Leuven, Leuven, Belgium; 6E.E.Dept, Katholieke Universiteit Leuven, Leuven, Belgium.
11:30 AM B3.10
Effect of Plasma Treatment and TMCTS Vapor Annealing on
the Reinforcement of Porous Low-k Films. Kazuo Kohmura1, Hirofumi Tanaka1, Shunsuke Oike1, Masami Murakami1, Tetsuo Ono1, Yutaka Seino2 and Takamaro Kikkawa2,3; 1MIRAI-ASET, Tsukuba, Japan; 2MIRAI-ASRC-AIST, Tsukuba, Japan; 3RCNS, Hiroshima, Japan.
11:45 AM B3.11
High Strength Low Dielectric Constant Aromatic Thermosets. Yongqing
Huang and James Economy; Materials Science and Engineering,
University of Illinois at Urbana-Champaign, Urbana, Illinois.
SESSION B4: Reliability of Low-K Dielectrics
Chair: Tom Shaw
Wednesday Afternoon, March 30, 2005
Room 2004 (Moscone West)
2:00 PM *B4.1
Constraint Effects on Cohesive Failures in Low-k Dielectric Thin Films. Ting Y. Tsui and Andrew J. McKerrow; Silicon Technology Development, Texas Instruments Inc, Dallas, Texas.
B4.2
ABSTRACT WITHDRAWN
B4.3
ABSTRACT WITHDRAWN
2:30 PM B4.4
Barrier Integrity Effect on Leakage Mechanism and Reliability of Copper/OSG Interconnects. Yunlong Li1,2, Zsolt Tokei1 and Karen Maex1,2; 1IMEC, Leuven, Belgium; 2Department of Electrical Engineering, Katholieke Universiteit, Leuven, Leuven, Belgium.
2:45 PM B4.5
Kinetics of Moisture-Induced Electrical Property Changes in Ordered Nanoporous Silica Low-k Dielectric Thin Films. A. P. Singh, P. Victor, P. G. Ganesan and G. Ramanath; Materials Science & Engineering, Rensselaer Polytechnic Institute, Troy, New York.
3:00 PM BREAK
SESSION B5: Copper Interconnects
Chair: Christine Hau-Riege
Wednesday Afternoon, March 30, 2005
Room 2004 (Moscone West)
3:30 PM *B5.1
Continued Scalability of Copper Low-k Interconnects. Sywert Hidde Brongersma1, Laureen Carbonell1, Kris Vanstreels2, Francesca Iacopi1, Jan D'Haen3, Wenqi Zhang1, Youssef Travaly1, Steven Demuynck1, Zsolt Tokei1, Ward DeCeuninck2,3 and Karen Maex1,4; 1SPDT/ITTO, IMEC, Leuven, VB, Belgium; 2Institute for Materials Research, Limburgs Universitair Centrum, Diepenbeek, Limburg, Belgium; 3IMOMEC, IMEC, Diepenbeek, Limburg, Belgium; 4E.E.Dept, Katholieke Universiteit Leuven, Leuven, VB, Belgium.
4:00 PM B5.2
Structure Evolution in Plated Cu Films. David P. Field1, No-Jin Park1,4, Paul R. Besser2 and John E. Sanchez3; 1Washington State Univ, Pullman, Washington; 2Advanced Micro Devices, Sunnyvale, California; 3Unity Semiconductor, Sunnyvale, California; 4Kumoh National Institute of Technology, Kumi, South Korea.
4:15 PM B5.3
Accelerated ECP Process Development with Automated Cu Grain Boundary Analysis Using SEMVision G2 FIB. Vicky Svidenko1, Roman M. Mostovoy2, Aron Rosenfeld2, Laurent Karsenti1 and Lior Levin1; 1PDC, Applied Materials, Inc., Santa Clara, California; 2TFG, Applied Materials, Inc., Santa Clara, California.
4:30 PM B5.4
The Effect of Temperature on Spontaneous Morphology Change in Electrodeposited Copper Metallization. Shafaat Ahmed1, D. N. Buckley1, S. Nakahara1 and Y. Kuo2; 1Department of Physics, Materials and Surface Science Institute,University of Limerick, Limerick, Ireland; 2Department of Chemical Engineering, Texas A&M University, College Station, Texas.
4:45 PM B5.5
Cu Resistivity in Narrow Lines: Effect of Metallization
Scheme. Sylvain Maitrejean1, Anne Roule1,
Jean-Frederic Guillaumond1,2, Murielle Fayolle1,
Anthony Roman2, Thierry Morel1, David
Bouchu1, Paul-Henry Haumesser1, Lucile
Arnaud1 and Gerad Passemard2; 1CEA-LETI,
Grenoble, France; 2STMicroelectronics, Crolles,
France.
SESSION B6: Barrier Metal Films
Chairs: Sywert Brongersma and David Field
Thursday Morning, March 31, 2005
Room 2004 (Moscone West)
8:30 AM B6.1
Atomic Layer Deposition (ALD) of Barrier/Adhesion/Seed Layers
for Interconnects. Zhengwen Li1, Huazhi
Li1, Youbo Lin2, Roy G. Gordon1 and
Joost J. Vlassak2; 1Chemistry and Chemical
Biology, Harvard University, Cambridge, Massachusetts; 2Engineering
and Applied Sciences, Harvard University, Cambridge, Massachusetts.
8:45 AM B6.2
MOCVD of Highly Conformal Cobalt Metal Films. Jeonggil
Lee, Heejung Yang and Jaegab Lee; School of Advanced Materials
Engineering, Kookmin University, Seoul, South Korea.
9:00 AM B6.3
Atomic Layer Deposition of Ruthenium Thin Films for the 45-nm Era. Jin Yong Kim1, Sang Yeol Kang1, Beom Seok Seo2, Jung Hyun Lee2, Kwanghee Lee1, Han Jin Lim1, Cha-Young Yoo1, Sung-Tae Kim1, U-In Chung1 and Joo-Tae Moon1; 1Process Development Team, Samsung Electronics Co., Ltd., Yongin-Si, Gyeonggi-Do, South Korea; 2Nano Fabrication Center, Samsung Advanced Institute of Technology, Yongin-Si, Gyeonggi-Do, South Korea.
9:15 AM B6.4
Plasma-Assisted Atomic Layer Deposition of TiN Films at Low Process Temperature in High-Aspect Ratio Structures. S. B. S. Heil1, E. Langereis1, F. Roozeboom2, A. Kemmeren2, N. P. Pham3, P. M. Sarro3, M. C. M. van de Sanden1 and W. M. M. Kessels1; 1Applied Physics, Eindhoven University of Technology, Eindhoven, Netherlands; 2Philips Research, Eindhoven, Netherlands; 3Delft University of Technology, Delft, Netherlands.
9:30 AM B6.5
Integration of ALD-TaN Liners on Nanoporous Dielectrics. Bum Ki Moon1, Tadashi Iijima2, Sandra Malhotra3, Andrew Simon3, Thomas Shaw3, E. Todd Ryan4, Cathy Labelle4, Nick Fuller3, Tibor Bolom4, Keishi Inoue5 and Vincent McGahay3; 1Infineon Technologies, NA, Corp., Hopewell Junction, New York; 2Toshiba America Electronic Components, Inc., Hopewell Junction, New York; 3IBM Microelectronics, Hopewell Junction, New York; 4AMD Corp., Hopewell Junction, New York; 5Sony Electronics Inc., Hopewell Junction, New York.
9:45 AM BREAK
10:15 AM B6.6
Effect of Dielectric Pore Size Distribution on Interfacial Adhesion of the Ta-Porous Dielectric Interface. Ravi Saxena1, Woojin Cho1, Oscar Rodriguez1, Ting Tsui2, Stephan Grunow2, William N. Gill1 and Joel Plawsky1; 1Chemical Engineering, Rensselaer Polytechnic Institute, Troy, New York; 2Texas Instruments, Dallas, Texas.
10:30 AM B6.7
ABSTRACT WITHDRAWN
10:45 AM B6.8
Managing Composition and Properties of CVD Boron Carbo-Nitride Films. P. Ryan Fitzpatrick1, Edward R. Engbrecht1,2 and John G. Ekerdt1; 1Chemical Engineering, Univ of Texas at Austin, Austin, Texas; 2Silicon Technology, Texas Instruments, Dallas, Texas.
11:00 AM B6.9
ABSTRACT WITHDRAWN
11:15 AM B6.10
Molecular Layers for Inhibiting In-Plane Surface/Interfacial Cu Diffusion in Damascene Interconnects. Chandrasekar Venkataramani1, P. G. Ganesan2, Anand V. Vairagar1,3, G. Ramanath2, Subodh G. Mhaisalkar1 and Ahila Krishnamoorthy3; 1School of Materials Engineering, Nanyang Technological University, Singapore, Singapore, Singapore; 2Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York; 3Semiconductor Process Technologies, Institute of Microelectronics, Singapore, Singapore.
11:30 AM B6.11
Diffusion Barrier Properties of Carboxyl- and Amine-Terminated
Molecular Nanolayers. P.G. Ganesan1,2,
A.P. Singh1 and G. Ramanath1; 1Department
of Materials Science and Engineering, Renesselaer Polytechnic
Institute, Troy, New York; 2Center for Integrated
Electronics, Renesselaer Polytechnic Institute, Troy, New York.
11:45 AM B6.12
Thermal Oxidation of Cu Interconnects Capped with CoWP. Jeff Gambino1, Sean Smith3, Steve Mongeon1, Dave Meatyard1, Fen Chen1 and Pat DeHaven2; 1IBM Microelectronics, Essex Junction, Vermont; 2IBM Microelectronics, Hopewell Junction, New York; 3IBM Thomas J. Watson Research Center, Yorktown Heights, New York.
SESSION B7/O11: Joint Session: Fatique and Stress in Interconnect Metallization
Chairs: Paul Besser and Ralph Spolenak
Thursday Afternoon, March 31, 2005
Room 2004 (Moscone West)
1:30 PM *B7.1/O11.1
Thermal Fatigue in Cu Films. Cynthia A. Volkert1,2, Reiner Moenig1,2, Erica Lilleodden1,2, Young Bae Park3,2 and Guang Ping Zhang4,2; 1Forschungszentrum Karlsruhe, Karlsruhe, Germany; 2Max-Planck-Institut fuer Metallforschung, Stuttgart, Germany; 3Andong National University, Andong, South Korea; 4Shenyang National Laboratory for Materials Science, Shenyang, China.
2:00 PM B7.2/O11.2
TEM-Based Analysis of Defects Induced by AC Thermomechanical
versus Microtensile Deformation in Aluminum Thin Films. Roy
H. Geiss, Robert R. Keller, David T. Read and Yi-Wen Cheng;
Materials Reliability, NIST, Boulder, Colorado.
2:15 PM B7.3/O11.3
Employing Thin Film Failure to Form Templates for Nano-Electronics. Rainer Adelung, Mady Elbahri, Shiva Kuma Rudra, Abhijit Biswas, Sahid Jebril, Rainer Kunz, Sebastian Wille and Michael Scharnberg; Materials Science, CAU Kiel, Kiel, Germany.
2:30 PM B7.4/O11.4
Degradation of Fracture and Fatigue Properties of MEMS Structures
under Cyclic Loading. Jong-jin Kim and Dongil Kwon;
School of Materials Science and Engineering, Seoul National
University, Seoul, South Korea.
2:45 PM B7.5/O11.5
Electrical and Mechanical Reliability of Cu Alloy Thin Film
for Future Technology Node. Seol-Min Yi1,
Jeong-Uk An1, Yong-Hak Huh2, Young-Bae
Park3 and Young-Chang Joo1; 1School
of Materials Science and Engineering, Seoul National University,
Seoul, South Korea; 2Strength Evaluation Group,
Korea Research Institute of Standards and Science, Deajeon,
South Korea; 3School of Materials Science & Engineering,
Andong National University, Andong-si, Kyungsangbukdo, South
Korea.
3:00 PM BREAK
3:30 PM *B7.6/O11.6
Effect of Microstructure and Dielectric Materials on Stress-Induced Damages in Damascene Cu/Low-K Interconnects. Young-Chang Joo and Jong-Min Paik; Materials Sci. & Eng., Seoul National University, Seoul, South Korea.
4:00 PM B7.7/O11.7
Comparison of Line Stress Predictions with Measured Electromigration Failure Times. Rao R. Morusupalli1, William D. Nix1, Jamshed R. Patel1,2 and Arief S. Budiman1; 1Materials Science and Engineering, Stanford University, Stanford, California; 2Advanced Light Source (ALS), Lawrence Berkeley National Laboratory (LBNL), Berkeley, California.
4:15 PM B7.8/O11.8
Stress-Induced Void Formation in Passivated Cu Film during
Thermal Cycling and Isothermal Annealing. Dongwen Gan, Bin Li and Paul S. Ho; Laboratory for Interconnect and Packaging, University of Texas at Austin, Austin, Texas.
4:30 PM B7.9/O11.9
Stress Generation in PECVD SiN Thin Films for Microelectronics Applications. Michael Belyansky1, Nancy Klymko1, Anita Madan1, Anu Mallikarjunan1, Ying Li1, Ashima Chakravarti1, Sadanand Deshpande1, Anthony Domenicucci1, Stephen Bedell1, Edward Adams1 and Sey-Ping Sun2; 1IBM Microelectronics, Hopewell Junction, New York; 2Advanced Micro Devices, Hopewell Junction, New York.
SESSION B8: Poster Session
Chairs: Francesca Iacopi, Andrew McKerrow, Hermann Oppermann and Joost Vlassak
Thursday Evening, March 31, 2005
8:00 PM
Salons 8-15 (Marriott)
B8.1
A Novel Organic Low-k Film Deposited by Plasma-Enhanced Co-Polymerization. Nobutaka Kunimi1, Jun Kawahara1, Akinori Nakano1, Keizo Kinoshita1, Masashi Komatsu1 and Takamaro Kikkawa2,3; 1MIRAI-ASET, Tsukuba, Japan; 2MIRAI-ASRC, AIST, Tsukuba, Japan; 3RCNS, Hiroshima Univ., Higashi-Hiroshima, Japan.
B8.2
Pure-Silica-Zeolite Low-k Films from Nanoparticle Suspension. Zijian
Li, Shaung Li, Christopher Lew and Yushan Yan; Chemical
and Environmental Engineering, University of California,
Riverside, Riverside, California.
B8.3
A New Methodology to Characterize and Model Cure Stress
in Packaging Based on a Thermal Expansion-Cure Shrinkage
Analogy. Hong Yu1, S. G. Mhaisalkar1 and
E. H. Wong2; 1School of Materials Engineering,
Nanyang Technological University, Singapore, Singapore; 2MicroSystems,
Modules & Components Lab, Institute of Microelectronics,
Singapore, Singapore.
B8.4
Mesoporous Low Dielectric Poly(silsesquioxane) Thin Films Templated by Various Surfactants. Jingyu Hyeon-Lee, Hyeon-jin Shin, Jong-baek Seon, Hyun-dam Jeong and Jongmin Kim; Samsung Advanced Institute of Technology, Suwon, South Korea.
B8.5
Spin-on Dielectric Materials for High Aspect Ratio Gap Fill for 70 nm Node and Beyond. Wei Chen, Sheng Wang, B. K. Hwang, Ather Ashraf and J. K. Lee; Dow Corning Corporation, Midland, Michigan.
B8.6
Annealing-Induced Adhesion Enhancement at Cu-SiO2 Interfaces Modified with Organosilane Nanolayers. Darshan D Gandhi, P. G. Ganesan, A. P. Singh and G. Ramanath; Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York.
B8.7
Post-Etch Measurement of Via Bottom Residues. Cecilia C. Martner, Peter Borden, Edgar Genio, Michael Wood, Jianshe Tang and Philip Fulmer; AMAT, Santa Clara, California.
B8.8
Pressure Dependent Parylene-N Pore Sealant Penetration
in Porous Low-k Dielectrics. Jasbir S. Juneja1,
Gregory A. Ten Eyck1, Hassa Bakhru2 and
Toh-Ming Lu1; 1Center of Integrated
Electronics, Rensselaer Polytechnic Institute, Troy, New
York; 2Department of Physics, SUNY, Albany, New
York.
B8.9
The Effect of Film Composition on the Properties of PECVD Low-k a-SiCO:H Films. Byung Keun Hwang, M. Tzou, A. Ashraf and B. Nguyen; Dow Corning Corporation, Midland, Michigan.
B8.10
New Carbon-Bridged Hybrid Polymer for Low-k Materials. Bum-gyu
Choi, Byung Ro Kim, Myung-sun Moon, Jungwon Kang,
Gwigwon Kang and Min-Jin Ko; LG Chem, Daejeon, South Korea.
B8.11
Development of Hermetic Oxide Films For Low k Pore Sealing. Kang Sub Yim, Vu Nguyen, B. H. Kim, Alex Demos, Girish Dixit, Derek Witty and Hichem MSaad; Applied Materials, Santa Clara, California.
B8.12
The Effect of Methylating Treatments on the Dielectric Reliability of Low-k/Cu Structures. Swarnal Borthakur1,2, Sri Satyanarayana1, Andreas Knorr1,3 and Paul S. Ho2; 1Sematech, Austin, Texas; 2The University of Texas at Austin, Austin, Texas; 3Infineon Technologies, Munich, Germany.
B8.13
Standard Porosimetry. Yury Volfkovich, Igor Blinov and Alexander Sakars; Porotech Ltd., Vaughan, Ontario, Canada.
B8.14
Capacitance Measurement Technique for Determining the Out-of-Plane Coefficient of Thermal Expansion for Low-k Dielectrics. Swarnal Borthakur1,2, Andreas Knorr1,3, Paul S. Ho2 and Wen-Li Wu4; 1Sematech, Austin, Texas; 2The University of Texas at Austin, Austin, Texas; 3Infineon Technologies, Munich, Germany; 4NIST, Gaithersburg, Maryland.
B8.15
Determination of Elastic Modulus and Yield Stress of Ultra-thin Cu and Low-k Films Using Spherical Nanoindentation Measurement. Satoshi Shimizu, Nobuo Kojima and Jiping Ye; Reserch Department, Nissan Arc, Ltd., Yokosuka, Japan.
B8.16
Adhesion Study of CVD Low-k Films to Si Substrate Using
4-point Bend and Nanoscratch Test. Martina Damayanti1,2,
Johnny Widodo2, Thirumany Sritharan1,
Subodh Gautam Mhaisalkar1, Wei Lu2,
Zhenghao Gan1, Kai Yang Zeng3 and Liang
Choo Hsia2; 1Materials Technology, Nanyang
Technological University, Singapore, Singapore; 2Technology
and Development Dept, Chartered Semiconductor Manufacturing
Ltd., Singapore, Singapore; 3Institute of Materials
Research and Engineering, Singapore, Singapore.
B8.17
Mechanical Strength Enhancement in Porous Silica Films by TMCTS Treatment. Nobutoshi Fujii1, Takahiro Nakayama1, Takenobu Yoshino2, Nobuhiro Hata2, Yutaka Seino2, Yuko Takasu2 and Takamaro Kikkawa2,3; 1MIRAI-ASET, Tsukuba, Japan; 2MIRAI-ASRC-AIST, Tsukuba, Japan; 3RCNS, Hiroshima Univ., Higashi-Hiroshima, Japan.
B8.18
Application of Nanoindentation to Characterize Fracture in ILD Films used in the BEOL. Eva Erika Simonyi, Eric Liniger, Michael Lane, Christos D. Dimitrakopoulos and Christy S. Tyberg; IBM TJ Watson RC, Yorktown Heights, New York.
B8.19
The Role of Friction and Loading Parameters in Four-Point Bend Adhesion Measurements. David M. Gage1, Kyunghoon Kim2, Christopher S. Litteken1 and Reinhold H. Dauskardt1; 1Materials Science and Engineering, Stanford University, Stanford, California; 2Mechanical Engineering, Stanford University, Stanford, California.
B8.20
ABSTRACT WITHDRAWN
B8.21
Rapid Characterization of the Electrical and Micro-Structural
Properties of Molybdenum-Tungsten Electrodes using a Combinatorial
Thin Film Sputtering Technique. Seung-Ik Jun1,
Timothy E. McKnight2, Anatoli V. Melechko2,1,
Michael L. Simpson1,2 and Philip D. Rack1; 1Materials
Science and Engineering, The University of Tennessee, Knoxville,
Tennessee; 2Molecular Scale Engineering and Nanoscale
Technologies Research Group, Oak Ridge National Laboratory,
Oak Ridge, Tennessee.
B8.22
Conducting Ruthenium Oxide Nano-Layers by UV-Ozone Oxidation. Vaishali
Ukirde1, Changduk Lim1, Oliver
Chyan2 and Mohamed El Bouanani1; 1Materials
Science, University of North Texas, Denton, Texas; 2Chemistry,
University Of North Texas, Denton, Texas.
B8.23
Advanced Al Damascene Process for Fine Trench under 70nm Design Rule. Sung Ho Han, Kyung-in Choi, Serah Yun, Jeong Heon Park, Sang Woo Lee, GilHeyun Choi, Sung Tae Kim, U-In Chung and Joo-Tae Moon; Samsung Electronic Co. Ltd., Yongin-City, Kyungki-Do, South Korea.
B8.24
A Study of Copper Electroplating in the Submicron Scale
Patterns. Ui-hyoung Lee, Hyo-Jong Lee and Tak
Kang; Material Science and Engineering, Seoul National University,
Seoul, South Korea.
B8.25
Modeling the Impact of Packaging Stress on Device Performance. Xiaopeng
Xu and Victor Moroz; TCAD R&D, Synopsys, Inc., Mountain
View, California.
B8.26
Material Reliability and Integration Issues of Benzocyclobutene (BCB) Interlayer Dielectric (ILD) Material. Parshuram Bakrishna Zantye1,2 and Ashok Kumar1,2; 1Department of Mechanical Engineering, University of South Florida, Tampa, Florida; 2Nanomaterials and Nanomanufacturing Research Center, University of South Florida, Tampa, Florida.
B8.27
Porosity Content Dependence of TDDB Lifetime and Flat-Band Voltage Shift by Cu Diffusion in Porous Spin-on Low-k. Sang-Soo Hwang1, Hee-Chan Lee1, Hyun Wook Ro2, Do Yeung Yoon2, Young-Bae Park3 and Young-Chang Joo1; 1School of Materials Science & Engineering, Seoul National University, Seoul, South Korea; 2School of Chemistry, Seoul National University, Seoul, South Korea; 3School of Material Science & Engineering, Andong National University, Andongsi, South Korea.
B8.28
Structure and Interfacial Reliability of Low Dielectric
Constant Organosilicate Glass (OSG) Thin Films. Youbo
Lin and Joost Vlassak; DEAS, Harvard University, Cambridge,
Massachusetts.
B8.29
Analysis of the Interfacial Reaction between Sn-3.5Ag and Electroplating Interlayers. Sheng-Min Yang1, Yinyu Chang2 and Weite Wu1; 1National Chung Hsing University, Taichung, Taiwan; 2Surftech Co, Taichung, Taiwan.
B8.30
Electromigration of Electroplated Gold Interconnects. Steve H. Kilgore1, Craig A. Gaw2, Haldane Henry2, Darrell Hill2 and Dieter K. Schroder3; 1Quality Organization, Freescale Semiconductor, Tempe, Arizona; 2Technology Solutions Organization, Freescale Semiconductor, Tempe, Arizona; 3Dept. of Electrical Engineering, Arizona State University, Tempe, Arizona.
B8.31
The Influence of Temperature, Structure, and Dielectric Materials on Stress Induced Voiding in Cu Dual-Damascene Interconnects. Wei Shao, Zhenghao Gan, Chandrasekar Venkataramanil, Subodh G. Mhaisalkar, Ahila Krishnamoorthy; School of Materials Engineering, Nanyang Technological University, Singapore.
SESSION B9: Interconnect Reliability Issues
Chairs: Paul Besser and Young-Chang Joo
Friday Morning, April 1, 2005
Room 2004 (Moscone West)
8:30 AM *B9.1
Passivation Effect on Stress Relaxation and Mass Transport in Electroplated Cu Films. Paul S. Ho1, Dongwen Gan1, Rui Huang1, Jihperng Leu2, Jose Maiz2 and Tracey Scherban2; 1Mechanical Engineering, The University of Texas at Austin, Austin, Texas; 2Intel Corporation, Hillsboro, Oregon.
9:00 AM B9.2
Fundamentals of Cu/Barrier Layer Adhesion in Microelectronic Processing. Harsono Simka1, Sadasivan Shankar1, Carolyn Duran2 and Michael Haverty1; 1Technology CAD - Logic Technology Development, Intel Corp., Santa Clara, California; 2Polymer Memory Group, Intel Corp., Hillsboro, Oregon.
9:15 AM B9.3
Effect of Current Direction on the Reliability of Different Capped Cu Interconnects. Chee Lip Gan1, Chin Yang Lee1, Cheng Kuo Cheng2 and Jeffrey Gambino3; 1School of Materials Engineering, Nanyang Technological University, Singapore, Singapore; 2Institute of Microelectronics, Singapore, Singapore; 3IBM Microelectronics, Essex Junction, Vermont.
9:30 AM B9.4
Multi-Via Electromigration Test Structures for Identification
and Characterization of Different Failure Mechanisms. Zung-Sun
Choi1, Choon Wai Chang2, Jung Hoon
Lee3, Chee Lip Gan4,2, Carl V. Thompson1,2,
Kin Leong Pey4,2 and Wee Kiong Choi5,2; 1Materials
Science and Engineering, MIT, Cambridge, Massachusetts; 2Materials
Science and Engineering, Singapore-MIT Alliance, Singapore,
Singapore; 3Electrical Engineering and Computer
Science, MIT, Cambridge, Massachusetts; 4Materials
Science and Engineering, Nanyang Technology University, Singapore,
Singapore; 5Materials Science and Engineering, National
University of Singapore, Singapore, Singapore.
9:45 AM B9.5
Microstructure Evolution during Electric Current Induced Thermomechanical Fatigue of Interconnects. Robert Keller1, Roy Geiss1, Yi-wen Cheng2 and David Read1; 1Materials Reliability Division, NIST, Boulder, Colorado; 2Protiro, Inc., Denver, Colorado.
10:00 AM BREAK
10:30 AM *B9.6
The Effect of Inter-Level Dielectric and Cap on the Electromigration Reliabiliity of CU Interconnects. Christine Hau-Riege1, Amit Marathe1 and Stefan Hau-Riege2; 1Technology and Reliability Development, AMD, Sunnyvale, California; 2Physics and Advanced Technologies, LLNL, Livermore, California.
11:00 AM B9.7
Characterization of Temporary Extrusion Failures in Quater-Micron
Copper Interconnects. Yan Zhang1, Jun-ho
Choy2, Glenn H. Chapman1 and Karen L.
Kavanagh2; 1Engineering School, Simon
Fraser University, Burnaby, British Columbia, Canada; 2Physics,
Simon Fraser University, Burnaby, British Columbia, Canada.
11:15 AM B9.8
Analysis of Electromigration-Induced Void Motion and Surface
Oscillation in Metallic Thin-Film Interconnects. Jaeseol
Cho, M. Rauf Gungor and Dimitrios Maroudas; Department
of Chemical Engineering, University of Massachusetts, Amherst,
Amherst, Massachusetts.
11:30 AM B9.9
The Effect of Immersion and Evaporated Sn Coating on the
Electromigration Failure Mechanism and Lifetimes of Cu Dual
Damascene Interconnects. Minyu Yan1, King Ning Tu1, Anand Vishwanath Vairagar2,3, Subodh Gautam Mhaisalkar2 and Ahila Krishnamoorthy3; 1Department of Materials Science and Engineering, UCLA, Los Angeles, California; 2School of Materials Engineering, Nanyang Technological University, Singapore, Singapore; 3Institute of Microelectronics, Singapore, Singapore.
11:45 AM B9.10
Synchrotron X-ray Micro-Diffraction Analysis on Microstructure
Evolution in Sn under Electromigration. Albert TzuChia
Wu1, KingNing Tu1, A. M. Gusak2,
J. R. Lloyd3, N. Tamura4 and C. R. Kao5; 1Materials
Science and Engineering, UCLA, Los Angeles, California; 2Theoretical
Physics, Cherkasy State University, Cherkasy, Ukraine; 3T.
J. Watson Research Center, IBM, Yorktown Heights, New York; 4Advanced
Light Source, Lawrence Berkeley National Laboratory, Berkeley,
California; 5Chemical & Materials Engineering, National
Central University, Chungli, Taiwan.
SESSION B10: Advanced Packaging Challenges
Chairs: Paul Ho and Ray Pearson
Friday Afternoon, April 1, 2005
Room 2004 (Moscone West)
1:30 PM *B10.1
Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps. Hermann Oppermann, Matthias Hutter, Gunter Engelmann and Herbert Reichl; Fraunhofer IZM, Berlin, Germany.
2:00 PM B10.2
Effect of Electromigration on Mechanical Behavior of Solder Joints. Fei Ren1, Jae-Woong Nah1, Jong-ook Suh1, Hua Gan1, King-Ning Tu1, Bingshou Xiong2, Luhua Xu2 and John H. Pang2; 1Materials Science and Engineering, Univ. of California, Los Angeles, Los Angeles, California; 2Mechanical and Production Engineering, Nanyang Technological University, Singapore, Singapore.
2:15 PM B10.3
Morphology and Flux-Driven Ripening of Cu6Sn5 Intermetallic Compound during Solder Reaction. Jong-ook Suh1, Andriy Gusak2 and King-Ning Tu1; 1Materials Science and Eng., Universitiy of California, Los Angeles, Los Angeles, California; 2Theoretical Physics, Cherkasy State University, Cherkasy, Ukraine.
2:30 PM B10.4
Development of C-Ring Technique for Studying Effect of Stress
on Growth of Interfacial Intermetallic Compounds. Wei Zhou, S. L. Ngoh and H. L. Pang; School of MPE, Nanyang Technological University, Singapore, Singapore.
2:45 PM B10.5
Micro-Impact Test on the Study of Failure Mode and Bonding Strength of BGA Balls and UBM Pad. Shengquan Ou, Yuhuan Xu and King-Ning Tu; Materials Science and Engineering, University of California, Los Angeles, Los Angeles, California.
3:00 PM BREAK
3:15 PM *B10.6
A New Approach for Predicting the Onset of Disbonds in Flip-Chip
Assemblies. Ray Pearson and Brian J. McAdams; Materials
Sci. & Eng., Lehigh University, Bethlehem, Pennsylvania.
3:45 PM B10.7
Low Temperature Ultra-Thin Titanium-Based Wafer Bonding. Jian Yu1, Yinmin Wang2, Hassa Bakhru3, Jian-Qiang Lu1 and Ronald J. Gutmann1; 1Rensselaer Polytechnic Institute, Troy, New York; 2Lawrence Livermore National Laboratory, Livermore, California; 3University of Albany-SUNY, Albany, New York.
4:00 PM B10.8
Effects of Bonding Process Parameters on Wafer-to-Wafer
Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer
Bonding. Frank Niklaus1, R. J. Kumar1,
J. J. McMahon1, J. Yu1, T. Matthias2,
M. Wimplinger3, P. Lindner3, J. -Q. Lu1,
T. S. Cale1 and R. J. Gutmann1; 1Focus
Center - New York, Rensselaer: Interconnections for Hyperintegration,
Rensselaer Polytechnic Institute, Troy, New York; 2EVGroup,
Schaerding, Austria; 3EVGroup Inc., Tempe, Arizona.
4:15 PM B10.9
Interconnects for Elastically Stretchable and Deformable
Electronic Surfaces. Joyelle Elizabeth Jones, Stephanie
P. Lacour and Sigurd Wagner; Electrical Engineering, Princeton
University, Princeton, New Jersey.
4:30 PM B10.10
High-Resolution Characterization of Buried Interfaces for Advanced Interconnect Architectures. Shriram Ramanathan1, Patrick Morrow1, Evan Pickett1, Yongmei Liu2 and Rajen Dias2; 1Components Research, Intel Corp., Portland, Oregon; 2Assembly Technology Development, Intel Corp., Chandler, Arizona.
4:45 PM B10.11
Scanning Near-Field Acoustic Holography (NFAH): Novel High Resolution Sub Surface Imaging for Embedded Features. Gajendra Shekhawat2, Ethan Young1 and Vinayak Dravid3; 1Material Science and Engineering, Northwestern University, Evanston, Illinois; 2Institute for Nanotechnology, Northwestern University, Evanston, Illinois; 3Material Science and Engineering, Northwestern University, Evanston, Illinois.
Symposium Organizers
Paul R. Besser
Advanced Micro Devices, Inc.
MS 36
One AMD Pl.
Sunnyvale, CA 94088
Tel: 408-749-2350
Fax: 408-774-8818
paul.besser@amd.com |
Andrew J. McKerrow
Texas Instruments, Inc.
MS 3736
13560 N. Central Expwy.
Dallas , TX 75243
Tel: 972-927-1017
Fax: 972-995-6383, mckerrow@ti.com |
C. P. Wong
Georgia Institute of Technology
School of Materials Science & Engineering
771 Ferst Dr. NW
Atlanta, GA 30332-0245
Tel: 404-894-8391
Fax: 404-894-9140
cp.wong@mse.gatech.edu |
Joost Vlassak
Harvard University
Pierce Hall 311
29 Oxford St.
Cambridge, MA 02138
Tel: 617-496-0424
Fax: 617-495-9837
vlassak@esag.harvard.edu |
Francesca Iacopi
IMEC
Kapeldreef 75
B-3001 Leuven, Belgium
Tel: 32-16-28-1846
Fax: 32-16-28-1214
francesca.iacopi@imec.be |
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